Memory system
AssigneeKioxia Corporation
InventorHisashi FUJIKAWA
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a memory system includes a nonvolatile memory chip, a buffer, and a controller. The nonvolatile memory chip includes a memory cell array. The buffer is capable of storing data received in accordance with receiving a write request from a host. In a case where a piece of data of a first size is written in a write operation for the nonvolatile memory chip, the controller performs a data transfer operation of transferring a piece of data of a second size smaller than the first size from the buffer to the nonvolatile memory chip multiple times. The controller writes, into the memory cell array, pieces of data of the second size transferred to the nonvolatile memory chip by performing the data transfer operation the multiple times, respectively.
Claims20
A memory system comprising:
- a nonvolatile memory chip including a memory cell array;
- a write buffer that is capable of storing data received in accordance with receiving a write request from a host;
- and
- a controller configured to:
- in a case where a piece of data of a first size is written in a write operation for the nonvolatile memory chip, perform a data transfer operation of transferring a piece of data of a second size from the write buffer to the nonvolatile memory chip multiple times, the second size being smaller than the first size;
- and
- write, into the memory cell array, pieces of data of the second size transferred to the nonvolatile memory chip by performing the data transfer operation the multiple times, respectively.
A memory system comprising:
- a nonvolatile memory chip comprising a first plane and a second plane, the first plane including a first memory cell array, a first latch circuit, and a second latch circuit, the second plane including a second memory cell array, a third latch circuit, and a fourth latch circuit;
- a write buffer that is capable of storing data received in accordance with receiving a write request from a host;
- and
- a controller configured to transmit, to the nonvolatile memory chip,
- a first command set that includes a first command to start data input, a first address indicative of a first block in the first memory cell array, first data to be written into the first block, and a second command to store the first data in the first latch circuit,
- a second command set that includes a third command to start data input, a second address indicative of a second block in the second memory cell array, second data to be written into the second block, and a fourth command to move the first data stored in the first latch circuit to the second latch circuit and to move the second data input in the third latch circuit to the fourth latch circuit,
- a third command set that includes a fifth command to start data input, a third address indicative of the first block, third data to be written into the first block, and a sixth command to store the third data in the first latch circuit, and
- a fourth command set that includes a seventh command to start data input, a fourth address indicative of the second block, fourth data to be written into the second block, and an eighth command to program the first data, the second data, the third data, and the fourth data into the first memory cell array and the second memory cell array.
Dependencies are inferred from the claim text.