Processing-in-memory (pim) high bandwidth memory (hbm) devices including pim dynamic random access memory (dram) dies

A memory device comprising:

• a plurality of banks, wherein each bank of the plurality of banks comprises:
• a plurality of sub cell blocks, wherein each of the plurality of sub cell blocks comprises a plurality of memory cells;
• a plurality of word lines;
• a plurality of bit lines;
• and
• a bank core circuit comprising:
• a row decoder connected to the plurality of memory cells via the plurality of word lines extending in a first horizontal direction;
• and
• a sense amplifier connected to the plurality of memory cells via the plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction, wherein the sense amplifier comprises a plurality of sense amplifier segments correspondingly connected to the plurality of sub cell blocks;
• a plurality of sub core circuits correspondingly connected to the plurality of sub cell blocks;
• and
• a first processing element connected to the plurality of sense amplifier segments and arranged in the first horizontal direction and configured to perform a logical operation on an operand comprising data loaded into the plurality of sense amplifier segments,
• wherein for each bank of the plurality of banks, the plurality of sub cell blocks form a cell array structure, and the bank core circuit forms a core peripheral circuit structure, and
• wherein for each respective bank of the plurality of banks, the cell array structure of the respective bank is disposed on the core peripheral circuit structure of the respective bank and overlaps the core peripheral circuit structure of the respective bank in a vertical direction.

A memory device comprising:

• a buffer die comprising an interface circuit configured to control data input and data output of the memory device;
• and
• a memory die stack disposed on the buffer die and comprising a stack of a plurality of memory dies,
• wherein each of the plurality of memory dies comprises:
• a plurality of banks, wherein each bank of the plurality of banks comprises:
• a plurality of sub cell blocks, wherein each of the plurality of sub cell blocks comprises a plurality of memory cells;
• a plurality of word lines;
• a plurality of bit lines;
• and
• a bank core circuit comprising:
• a row decoder connected to the plurality of memory cells via the plurality of word lines extending in a first horizontal direction, wherein the row decoder comprises a plurality of sub word line driver segments;
• a sense amplifier connected to the plurality of memory cells via the plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction, wherein the sense amplifier comprises a plurality of sense amplifier segments;
• and
• a plurality of sub core circuits comprising a first processing element, a sub word line driver segment of the plurality of sub word line driver segments, and a sense amplifier segment of the plurality of sense amplifier segments, wherein the first processing element and the sense amplifier segment of each sub core circuit of the plurality of sub core circuits are connected,
• wherein the plurality of sub core circuits of a given bank of the plurality of banks are correspondingly connected to the plurality of sub cell blocks of the given bank of the plurality of banks,
• wherein for each bank of the plurality of banks, the plurality of sub cell blocks form a cell array structure, and the bank core circuit forms a core peripheral circuit structure,
• wherein for each respective bank of the plurality of banks, the cell array structure of the respective bank is disposed on the core peripheral circuit structure of the respective bank and overlaps the core peripheral circuit structure of the respective bank in a vertical direction, and
• wherein each sub core circuit of the plurality of sub core circuits of each respective bank of the plurality of banks is configured to perform a logical operation on an operand comprising data loaded into the plurality of sense amplifier segments of the respective bank core circuit.