Dynamic DDR Scaling And Use Case Management Based On DDR Refresh Rate And Size

A computing device, comprising:

• a memory frequency device configured to:
• compare at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between a memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC;
• select a memory frequency based on a result of the comparison;
• and
• configure the memory for the memory frequency.

A computing device, comprising:

• means for comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between a memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC;
• means for selecting a memory frequency based on a result of the comparison;
• and
• means for configuring the memory for the memory frequency.

A non-transitory processor-readable medium having stored thereon processor executable instructions configured to cause a memory frequency device of a computing device to perform operations comprising:

• comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between a memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC;
• selecting a memory frequency based on a result of the comparison;
• and
• configuring the memory for the memory frequency.