Semiconductor device and semiconductor diagnostic device

A semiconductor diagnostic device that diagnoses a first semiconductor circuit, comprising:

• a counter circuit configured to count in synchronization with a first clock signal and generate a readout signal when the count reaches a predetermined number;
• a buffer configured to store test data and sequentially output the test data in the order stored in synchronization with the first clock signal when the readout signal indicates a valid value;
• a first scan test circuit that sequentially captures the test data output from the buffer in synchronization with the first clock signal;
• an input terminal;
• a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a second clock signal;
• an output terminal;
• a transmission circuit that outputs the test data output by the first scan test circuit to the output terminal in synchronization with the second clock signal;
• a first test device;
• and
• a second test device comprising:
• an output terminal connected to the input terminal of the first semiconductor circuit;
• a transmission circuit that outputs the test data input from the first test device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal;
• a counter circuit configured to count in synchronization with the third clock signal and generate a readout signal when the count reaches a predetermined number;
• a buffer configured to store test data and sequentially output the test data in synchronization with the third clock signal when the readout signal indicates a valid value;
• an input terminal connected to the output terminal of the first semiconductor circuit;
• a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with the fourth clock signal;
• and
• an output terminal from which the test data from the buffer is output.

A semiconductor device comprising:

• a first semiconductor circuit includes:
• a counter circuit configured to count in synchronization with a first clock signal and generate a readout signal when the count reaches a predetermined number,
• a buffer configured to store test data and sequentially output the test data in the order stored in synchronization with the first clock signal when the readout signal indicates a valid value,
• a debug interface that sequentially captures the test data output from the buffer in synchronization with the first clock signal, an input terminal,
• a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with a second clock signal,
• an output terminal,
• and a transmission circuit that outputs the test data output by the debug interface to the output terminal in synchronization with the second clock signal;
• and
• a second semiconductor circuit includes:
• an output terminal connected to the input terminal of the first semiconductor circuit,
• a transmission circuit that outputs test data input from a debug device in synchronization with a third clock signal to the output terminal in synchronization with a fourth clock signal,
• a counter circuit configured to count in synchronization with the third clock signal and generate a readout signal when the count reaches a predetermined number,
• a buffer configured to store test data and sequentially output the test data in the order stored in synchronization with the third clock signal when the readout signal indicates a valid value,
• an input terminal connected to the output terminal of the first semiconductor circuit,
• a reception circuit that sequentially writes the test data input to the input terminal into the buffer in synchronization with the fourth clock signal, and
• an output terminal from which the test data from the buffer is output.