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US 2025/0053190 A1Published application
Clock distribution network, and semiconductor apparatus and semiconductor system using the clock distribution network
AssigneeSK hynix Inc.
InventorJi Hyo KANG
Life of this patent
Estimating the term…
Abstract
A clock distribution network includes an input control circuit and a clock tree. The input control circuit is configured to generate a control input clock signal based on an input clock signal and a low power mode signal. The clock tree is configured to generate an output clock signal by buffering the control input clock signal. When the low power mode signal is enabled, the input control circuit is configured to change a DC level of the control input clock signal.
Claims26
A clock distribution network comprising:
- an input control circuit configured to receive an input clock signal and a low power mode signal to generate a control input clock signal and a level signal, to output the input clock signal as a control input clock signal when the low power mode signal is disabled, to output the level signal as the control input clock signal when the low power mode signal is enabled, and to alternately change a direct current (DC) level of the level signal to a first level and a second level each time the low power mode signal is enabled;
- and
- a clock tree configured to receive the control input clock signal to generate an output clock signal by buffering the control input clock signal.
A semiconductor apparatus comprising:
- a global input control circuit configured to receive a system clock signal and a global enable signal to output the system clock signal as a control system clock signal when the global enable signal is enabled, to fix a logic level of the control system clock signal when the global enable signal is disabled, and to change a direct current (DC) level of the control system clock signal whenever the global enable signal is disabled;
- and
- a global clock tree configured to receive the control system clock signal to generate a first global clock signal by buffering the control system clock signal.
A clock distribution network comprising:
- an input control circuit configured to receive an enable signal and an input clock signal to generate a level signal by dividing the enable signal, and to output one of the level signal and an input clock signal as a control input clock signal based on the enable signal;
- and
- a clock tree configured to receive the control input clock signal to generate an output clock signal by buffering the control input clock signal.
A semiconductor apparatus comprising:
- a global input control circuit configured to receive a system clock signal and a global enable signal to generate a first level signal by dividing the global enable signal, and to output one of the first level signal and the system clock signal as a control system clock signal based on the global enable signal;
- and
- a global clock tree configured to receive the control system clock signal to generate a first global clock signal by buffering the control system clock signal.
Dependencies are inferred from the claim text.