Device, method and system for in-field lane testing and repair with a three-dimensional integrated circuit

A method comprising:

• receiving, at a test unit of a first integrated circuit (IC) die, status information from a power management control (PMC) agent, wherein the first IC die and a second IC die are coupled to form, at least in part, a three-dimensional (3D) IC, wherein the test unit receives the status information during an in-field operation of the 3D IC;
• based on the status information, detecting a first condition wherein a first partition of the first IC die, and a second partition of the second IC die, are each in a respective idle state, wherein the 3D IC comprises a first lane between the first partition and the second partition;
• detecting a second condition wherein one or more communications via the first lane fail to satisfy a performance criteria;
• based on the second condition, and during the first condition:
• disabling a first conductive path between the first lane and the first partition;
• and
• enabling a second conductive path between a second lane of the 3D IC and the first partition.

A system comprising:

• a first integrated circuit (IC) die and a second IC die coupled to each other to form, at least in part, a three-dimensional (3D) IC, wherein the first IC die comprises:
• a test unit to receive status information from a power management control (PMC) agent during an in-field operation of the 3D IC, the test unit further to:
• detect, based on the status information, a first condition wherein a first partition of the IC die, and a second partition of the other IC die, are each in a respective idle state, wherein the 3D IC comprises a first lane between the first partition and the second partition;
• and
• detect a second condition wherein one or more communications via the first lane fail to satisfy a performance criteria;
• and
• mode circuitry coupled to the test unit;
• wherein, based on the second condition, and during the first condition, the test unit is to signal the mode circuitry to disable a first conductive path between the first lane and the first partition, and further to enable a second conductive path between a second lane of the 3D IC and the first partition;
• and
• a memory interface to communicate a signal between the 3D IC and a memory.