Systems, apparatuses, and methods for on chip dynamic ir drop oscilloscope

An apparatus comprising:

• an oscilloscope circuitry comprising:
• a sensor circuitry including a sample and hold circuitry and a sense amplifier circuitry, wherein the sample and hold circuitry is configured to generate a plurality of samples based at least on a voltage waveform;
• a voltage generation circuitry including an output coupled to the sense amplifier circuitry, wherein the output is configured to provide a reference voltage;
• a finite state machine coupled to the sensor circuitry and the voltage circuitry, wherein the finite state machine is configured to operate the sensor circuitry and voltage generation circuitry to compare the plurality of samples to the reference voltage and generate a plurality of flags, wherein comparing of each of the plurality of samples to the reference voltage generates a flag of the plurality of flags when the sample exceeds the reference voltage;
• a latch circuitry coupled to the finite state machine, wherein the latch circuitry is configured to store a plurality of outputs generated based on the flag;
• and
• a display configured to render the stored plurality of outputs as a waveform.

A method comprising:

• sampling a voltage waveform to generate a plurality of samples with a sample and hold circuitry;
• transmitting the plurality of samples from the sample and hold circuitry to a sense amplifier circuitry;
• generating, by a voltage generation circuitry, a reference voltage;
• transmitting the reference voltage from the voltage generator circuitry to the sense amplifier circuitry;
• comparing, by the sense amplifier circuitry, the plurality of samples to the reference voltage based at least on a plurality of sensor compare signals generated by a finite state machine;
• generating, by the sense amplifier circuitry, one or more flags based on the comparing of the plurality of samples to the reference voltage when each sample of the plurality of samples exceeds the reference voltage;
• storing, by latching circuitry, a plurality of outputs generated based on the one or more flags;
• a latch circuitry coupled to the finite state machine, wherein the latch circuitry is configured to store a plurality of outputs generated based on the flag.