Pixel circuits for liquid crystal on silicon phase modulator
AssigneeOhio State Innovation Foundation
InventorsChongchang MAO, Lianhua JI, Kristina JOHNSON
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AssigneeOhio State Innovation Foundation
InventorsChongchang MAO, Lianhua JI, Kristina JOHNSON
Estimating the term…
Disclosed herein is a frame buffer pixel circuit having a first data pass gate transistor G1, first storage capacitor C1, a voltage boosting line Vb, source follower transistor F, pull-down transistor P, and second data pass gate transistor G2. The pull-down transistor P is connected to the drain of transistor F and source of transistor G2 and the storage capacitor C1 is connected to a voltage boosting line Vb. In the operation, Vb is set to zero volt when data is transferring to C1 capacitor through G1 gate. After the frame data are loaded onto C1 capacitors in all pixels, Vb is set to designed voltage and G2 gates in all pixels are opened to charge Clcd capacitors. Vb is then set to zero volt again before starting to load next frame data onto pixels. Such process is iterated in the liquid crystal on silicon (LCOS) working time.
A circuit of controlling a pixel electrode of a liquid crystal on silicon backplane phase modulator, comprising:
A circuit for controlling a pixel electrode of a liquid crystal on silicon phase modulator, comprising:
A circuit for controlling a pixel electrode of a liquid crystal on silicon phase modulators is composed of a data line, two data transfer controllers, two storage units that are connected to two voltage boosters, and two amplification circuits;
A system for controlling a pixel electrode of a liquid crystal on silicon backplane phase modulator, the system comprising:
A system for controlling a pixel electrode of a liquid crystal on silicon phase modulator, the system comprising:
A system for controlling a pixel electrode of a liquid crystal on silicon phase modulators, the system comprising:
Dependencies are inferred from the claim text.