Sharding for synchronous processors
AssigneeGoogle Inc.
InventorsReiner Pope, Herman Schmit, Michial Allen Gunter
Life of this patent
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Abstract
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.
Claims20
A method comprising:
- receiving a representation of a dataflow graph indicating matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- determining, based on a resource constraint of the hardware integrated circuit, a minimum compute time to execute the matrix operations using the plurality of synchronous tiles;
- generating, based on the minimum compute time, an allocation that assigns respective portions of the matrix operations to each of the plurality of synchronous tiles of the hardware integrated circuit;
- and
- generating, based on the allocation, hardware instructions that cause the hardware integrated circuit to synchronize executing the respective portions of the matrix operations across the plurality of synchronous tiles.
A system comprising:
- a processing device;
- and
- a non-transitory machine-readable storage device storing instructions that are executable by the processing device to cause performance of operations comprising:
- receiving a representation of a dataflow graph indicating matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- determining, based on a resource constraint of the hardware integrated circuit, a minimum compute time to execute the matrix operations using the plurality of synchronous tiles;
- generating, based on the minimum compute time, an allocation that assigns respective portions of the matrix operations to each of the plurality of synchronous tiles of the hardware integrated circuit;
- and
- generating, based on the allocation, hardware instructions that cause the hardware integrated circuit to synchronize executing the respective portions of the matrix operations across the plurality of synchronous tiles.
A non-transitory machine-readable storage device storing instructions that are executable by a processing device to cause performance of operations comprising:
- receiving a representation of a dataflow graph indicating matrix operations to be performed by a hardware integrated circuit comprising a plurality of synchronous tiles;
- determining, based on a resource constraint of the hardware integrated circuit, a minimum compute time to execute the matrix operations using the plurality of synchronous tiles;
- generating, based on the minimum compute time, an allocation that assigns respective portions of the matrix operations to each of the plurality of synchronous tiles of the hardware integrated circuit;
- and
- generating, based on the allocation, hardware instructions that cause the hardware integrated circuit to synchronize executing the respective portions of the matrix operations across the plurality of synchronous tiles.
Dependencies are inferred from the claim text.