Display panel, manufacturing method of display panel, and display device

A display panel, comprising:

• a substrate;
• an array circuit layer located on the substrate and comprising a plurality of drive transistors;
• a pixel defining layer and a plurality of sub-pixel units, wherein the pixel defining layer and the plurality of sub-pixel units are located on a side of the array circuit layer facing away from the substrate, each of the plurality of sub-pixel units comprises a first electrode, the pixel defining layer comprises a plurality of pixel defining portions and an opening region formed by enclosing the plurality of pixel defining portions, and the first electrode is exposed outside the opening region;
• a first capacitor comprising a first pole plate and a second pole plate, wherein an orthographic projection of the first pole plate on the substrate at least partially overlaps with an orthographic projection of the second pole plate on the substrate, and the first pole plate is connected to a gate of a drive transistor of the plurality of drive transistors;
• and
• an isolation portion located on a side of the substrate, wherein the isolation portion is disposed at least partially around the opening region, an orthographic projection of the isolation portion on the substrate at least partially overlaps with the orthographic projection of the first pole plate on the substrate, and at least part of the isolation portion is also served as the second pole plate.

A display device, comprising a display panel,

• wherein the display panel comprises:
• a substrate;
• an array circuit layer located on the substrate and comprising a plurality of drive transistors;
• a pixel defining layer and a plurality of sub-pixel units, wherein the pixel defining layer and the plurality of sub-pixel units are located on a side of the array circuit layer facing away from the substrate, and each of the plurality of sub-pixel units comprises a first electrode;
• and
• a first capacitor comprising a first pole plate and a second pole plate, wherein the first pole plate is disposed on a same layer as the first electrode, the pixel defining layer covers the first pole plate, the second pole plate is located on a side of the pixel defining layer facing away from the substrate, an orthographic projection of the first pole plate on the substrate at least partially overlaps with an orthographic projection of the second pole plate on the substrate, and the first pole plate is connected to a gate of a drive transistor of the plurality of drive transistors;
• or,
• wherein the display panel comprises:
• a substrate;
• an array circuit layer located on the substrate and comprising a plurality of drive transistors;
• a pixel defining layer and a plurality of sub-pixel units, wherein the pixel defining layer and the plurality of sub-pixel units are located on a side of the array circuit layer facing away from the substrate, each of the plurality of sub-pixel units comprises a first electrode, the pixel defining layer comprises a plurality of pixel defining portions and an opening region formed by enclosing the plurality of pixel defining portions, and the first electrode is exposed outside the opening region;
• a first capacitor comprising a first pole plate and a second pole plate, wherein an orthographic projection of the first pole plate on the substrate at least partially overlaps with an orthographic projection of the second pole plate on the substrate, and the first pole plate is connected to a gate of a drive transistor of the plurality of drive transistors;
• and
• an isolation portion located on a side of the substrate, wherein the isolation portion is disposed at least partially around the opening region, an orthographic projection of the isolation portion on the substrate at least partially overlaps with the orthographic projection of the first pole plate on the substrate, and at least part of the isolation portion is also served as the second pole plate.