Array Substrate and Preparation Method Thereof, and Display Device

A preparation method of an array substrate, the array substrate comprising a substrate and a plurality of pixel circuits distributed in an array on the substrate, the pixel circuit comprising at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor, wherein the array substrate comprises a first semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second semiconductor layer, a third insulating layer, a second metal layer, a fourth insulating layer and a third metal layer sequentially formed on the substrate, wherein the first semiconductor layer comprises a first conductive area, a second conductive area, and a first channel area between the first conductive area and the second conductive area, in which a source and a drain of the low-temperature polysilicon thin film transistor are respectively coupled to the first conductive area and the second conductive area by patterning the first metal layer and forming a gate of the low-temperature polysilicon thin film transistor;

• the second semiconductor layer comprises a third conductive area, a fourth conductive area, and a second channel area between the third conductive area and the fourth conductive area, in which a source and a drain of the oxide thin film transistor are respectively coupled to the third conductive area and the fourth conductive area by patterning the second metal layer and forming a gate of the oxide thin film transistor;
• the second insulating layer, the third insulating layer, and the fourth insulating layer are respectively provided with via holes aligned in a thickness direction, and the third metal layer is electrically connected to the second metal layer and the first metal layer through the via holes, in which the third metal layer is made of a low-resistance material, the preparation method comprising:
• forming the patterned first semiconductor layer on the substrate;
• depositing the first insulating layer on the first semiconductor layer;
• depositing the patterned first metal layer on the first insulating layer, and etching the first metal layer to form the gate of the low-temperature polysilicon thin film transistor;
• performing conducting treatment on the first semiconductor layer, wherein an area covered by the gate of the low-temperature polysilicon thin film transistor is a first channel area, two sides of the first channel area are the first conductive area and the second conductive area, and the source and the drain of the low-temperature polysilicon thin film transistor are respectively coupled to the first conductive area and the second conductive area;
• depositing the second insulating layer on the first metal layer;
• forming the patterned second semiconductor layer on the second insulating layer;
• depositing the third insulating layer on the second semiconductor layer;
• depositing the patterned second metal layer on the third insulating layer, and etching the second metal layer to form the gate of the oxide thin film transistor;
• performing conducting treatment on the second semiconductor layer, wherein an area covered by the gate of the oxide thin film transistor is a second channel area, two sides of the second channel area are the third conductive area and the fourth conductive area, and the source and the drain of the oxide thin film transistor are respectively coupled to the third conductive area and the fourth conductive area;
• depositing the fourth insulating layer on the second metal layer, and
• forming a plurality of via holes on the fourth insulating layer, the third insulating layer, and the second insulating layer;
• and
• depositing the patterned third metal layer on the fourth insulating layer, wherein the third metal layer is electrically connected to the second metal layer and the first metal layer through the via holes and is made of a low-resistance material.

A display device comprising:

• an array substrate comprising a substrate and a plurality of pixel circuits distributed in an array on the substrate, the pixel circuit comprising at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor, wherein
• the array substrate comprises a first semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second semiconductor layer, a third insulating layer, a second metal layer, a fourth insulating layer and a third metal layer sequentially formed on the substrate, the first semiconductor layer comprises a first conductive area, a second conductive area, and a first channel area between the first conductive area and the second conductive area, a source and a drain of the low-temperature polysilicon thin film transistor are respectively coupled to the first conductive area and the second conductive area by patterning the first metal layer and forming a gate of the low-temperature polysilicon thin film transistor;
• the second semiconductor layer comprises a third conductive area, a fourth conductive area, and a second channel area between the third conductive area and the fourth conductive area, a source and a drain of the oxide thin film transistor are respectively coupled to the third conductive area and the fourth conductive area by patterning the second metal layer and forming a gate of the oxide thin film transistor, the second insulating layer, the third insulating layer, and the fourth insulating layer are respectively provided with via holes aligned in a thickness direction, the third metal layer is electrically connected to the second metal layer and the first metal layer through the via holes, and the third metal layer is made of a low-resistance material.