Array substrate and display panel

An array substrate, comprising an underlay substrate and a plurality of sub-pixels arranged in an array on the underlay substrate;

• wherein each of the sub-pixels at least comprises a first transistor, a second transistor, and a storage capacitor;
• wherein a drain electrode of the first transistor is connected to a gate electrode of the second transistor, and the drain electrode of the first transistor is connected to a first electrode plate of the storage capacitor;
• wherein a drain electrode of the second transistor is connected to a second electrode plate of the storage capacitor, the second electrode plate and the first electrode plate are disposed opposite to each other, and the second electrode plate is located on a side of the first electrode plate away from the underlay substrate;
• wherein the array substrate further comprises
• a first scan line extending along a first direction and a data line and a first power line extending along a second direction, a source electrode of the first transistor is connected to the data line, a gate electrode of the first transistor is connected to the first scan line, and a source electrode of the second transistor is connected to the first power line;
• a first metal layer disposed on a side of the underlay substrate, wherein the first metal layer comprises the first electrode plate and the first power line;
• a buffer layer covering the first metal layer away from a side of the underlay substrate;
• a semiconductor layer disposed on a side of the buffer layer away from the first metal layer, wherein the semiconductor layer comprises a first active portion of the first transistor, a second active portion of the second transistor, and the second electrode plate;
• a gate electrode insulation layer covering the semiconductor layer and the buffer layer;
• and
• a second metal layer disposed on a side of the gate electrode insulation layer away from the semiconductor layer, wherein the second metal layer comprises a gate electrode of the first transistor, a gate electrode of the second transistor, and the first scan line;
• wherein the first electrode plate is connected between the gate electrode of the second transistor and the drain electrode of the first transistor;
• wherein the array substrate further comprises a detective signal line extending along the second direction;
• and the sub-pixel further comprises a third transistor, a source electrode of the third transistor is connected to the detective signal line, and a drain electrode of the third transistor is connected to the drain electrode of the second transistor and the second electrode plate.