Semiconductor device and a method of manufacturing the same

A semiconductor device comprising:

• a substrate;
• a first logic cell on the substrate;
• a second logic cell on the substrate and spaced apart from the first logic cell in a first direction;
• and
• a dummy region between the first logic cell and the second logic cell,
• wherein the first logic cell comprises:
• a first source/drain pattern;
• and
• a first channel pattern connected to the first source/drain pattern,
• wherein the first channel pattern comprises a plurality of semiconductor patterns vertically stacked and spaced apart from each other,
• wherein the dummy region comprises:
• an insulating pattern on the substrate;
• a seed pattern on the insulating pattern;
• and
• a seed mask pattern at least partially covering a top surface of the seed pattern and a first sidewall of the seed pattern, and
• wherein the top surface of the seed pattern is a level that is higher than a level of a top surface of an uppermost semiconductor pattern of the plurality of semiconductor patterns.

A semiconductor device comprising:

• a substrate;
• a first device region on the substrate;
• a second device region on the substrate and spaced apart from the first device region in a first direction;
• a first dummy region between the first device region and the second device region;
• and
• an insulating pattern in the first device region, the second device region and the first dummy region,
• wherein the first dummy region comprises:
• a seed pattern provided on the insulating pattern;
• and
• a seed mask pattern at least partially covering a top surface of the seed pattern and extending from the top surface of the seed pattern along a first sidewall of the seed pattern,
• wherein each of the first device region and the second device region comprises:
• an active pattern on the substrate, wherein the insulating pattern in the first device region and the second device region is on respective active patterns of the first device region and the second device region;
• source/drain patterns on the insulating pattern;
• channel patterns on the insulating pattern and connected to the source/drain patterns, each of the channel patterns comprising a plurality of semiconductor patterns vertically stacked and spaced apart from each other;
• gate electrodes respectively on the channel patterns, the gate electrodes extending parallel to each other in a second direction that is perpendicular to the first direction;
• and
• active contacts respectively connected to the source/drain patterns,
• wherein the plurality of semiconductor patterns comprise a material that is the same as a material of the seed pattern,
• wherein the seed pattern comprises a second sidewall opposite the first sidewall and that is exposed by the seed mask pattern, and
• wherein the second sidewall forms an acute angle with a top surface of the insulating pattern.