Stacked field effect transistor hybrid gate cut

Abstract

A semiconductor device including a stacked structure including first vertically stacked channel regions positioned over second vertically stacked channel regions. The first and second vertically stacked channel regions have a mid dielectric layer positioned therebetween. A structure is present having a first portion in electrical communication with the first vertically stacked channel regions and a second portion in electrical communication with the second vertically stacked channel regions. The semiconductor device also includes at least one two-component gate cut structure present adjacent to the gate all around structure. A first component of the two-component gate cut structure in positioned on one side of the mid dielectric layer adjacent to the first portion of the gate structure, and a second component of the two-component gate cut structure is positioned on a second side of the mid dielectric layer adjacent to the second portion of the gate structure.

Dependencies are inferred from the claim text.