Stacked transistor channel regions and methods of forming the same

A device comprising:

• lower semiconductor nanostructures comprising a first semiconductor material;
• a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type;
• upper semiconductor nanostructures comprising a second semiconductor material, the second semiconductor material different from the first semiconductor material;
• and
• an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.

A method comprising:

• forming lower semiconductor nanostructures, lower dummy nanostructures, upper semiconductor nanostructures, and upper dummy nanostructures, the lower semiconductor nanostructures and the upper dummy nanostructures formed of a first semiconductor material, the upper semiconductor nanostructures and the lower dummy nanostructures formed of a second semiconductor material;
• replacing the lower dummy nanostructures with lower dielectric structures, the lower dielectric structures formed of a first dielectric material;
• replacing the upper dummy nanostructures with upper dielectric structures, the upper dielectric structures formed of the first dielectric material;
• and
• removing the lower dielectric structures and the upper dielectric structures with an etching process that selectively etches the first dielectric material at a faster rate than the first semiconductor material and the second semiconductor material.