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US 2025/0040236 A1Published application
Semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorJunji IWAHORI
Life of this patent
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Abstract
A standard cell includes: a gate interconnect; a dummy gate interconnect formed to be adjacent to the gate interconnect on the right side of the gate interconnect in the figure in the X direction; a pad provided between the gate interconnect and the dummy gate interconnect; a nanosheet formed to overlap the gate interconnect as viewed in plan and connected with the pad; and a dummy nanosheet formed to overlap the dummy gate interconnect as viewed in plan and connected with the pad.
Claims6
A semiconductor integrated circuit device comprising:
- a first transistor;
- a second transistor;
- a first dummy gate interconnect;
- and
- a first dummy nanosheet, wherein
- the first transistor includes:
- a first gate interconnect;
- a first nanosheet formed to overlap the first gate interconnect as viewed in plan;
- and
- a first pad connected with the first nanosheet,
- the second transistor includes:
- a second gate interconnect;
- a second nanosheet formed to overlap the second gate interconnect as viewed in plan;
- and
- a second pad connected with the second nanosheet,
- the first and second transistors are arranged side by side in a first direction,
- the first dummy gate interconnect is formed to be adjacent to the first gate interconnect on a side of the first gate interconnect closer to the second gate interconnect in the first direction, and
- the first dummy nanosheet is formed to overlap the first dummy gate interconnect as viewed in plan and is connected with the first pad.
15 more elements
Dependencies are inferred from the claim text.