Integrated circuit device and manufacturing method thereof

A method for manufacturing an integrated circuit device, comprising:

• depositing an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first and second semiconductor layers alternatively arranged over the semiconductor substrate;
• patterning the epitaxial stack to form a semiconductor fin;
• forming a dummy gate structure over the semiconductor fin, wherein the dummy gate structure comprises a dummy gate dielectric layer and a dummy gate electrode over the dummy gate dielectric layer;
• removing a first portion of the dummy gate electrode and a first portion of the dummy gate dielectric layer to expose a first side of the semiconductor fin, wherein a second side of the semiconductor fin is covered by a second portion of the dummy gate dielectric layer;
• removing the first semiconductor layers in the semiconductor fin, while leaving the second semiconductor layers, wherein ends of the second semiconductor layers adjoins the second portion of the dummy gate dielectric layer;
• after removing the first semiconductor layers in the semiconductor fin, trimming the second portion of the dummy gate dielectric layer;
• and
• forming a high-k/metal gate structure around the second semiconductor layers.

An integrated circuit device, comprising:

• a plurality of first channel layers vertically spaced apart from each other;
• a plurality of second channel layers vertically spaced apart from each other;
• a first gate structure surrounding the first channel layers and the second channel layers, wherein the first gate structure comprises a gate dielectric layer and a gate metal layer over the gate dielectric layer;
• and
• a dielectric feature in the first gate structure, wherein the dielectric feature is between the first channel layers and the second channel layers, and the gate metal layer has a first portion below the dielectric feature.