Method for forming layout pattern of static random access memory

A method for forming a layout pattern of a static random access memory (SRAM), comprising:

• forming a plurality of fin structures located on a substrate;
• forming a plurality of gate structures located on the substrate, wherein the plurality of gate structures span the plurality of fin structures, to form a PU1 (first pull-up transistor), a PU2 (second pull-up transistor), a PDIA (first pull-down transistor), a PD1B (second pull-down transistor), a PD2A (third pull-down transistor), a PD2B (fourth pull-down transistor), a PGIA (first access transistor), a PG1B (second access transistor), a PG2A (third access transistor) and a PG2B (fourth access transistor) on the substrate, wherein the PD1A and the PD1B are connected in parallel, and the PD2A and the PD2B are connected in parallel;
• wherein the plurality of gate structures include a first J-shaped gate structure, the first J-shaped gate structure spans a part of the fin structures and forms the PU1, the PDIA and the PD1B, the first J-shaped gate structure comprises a long side structure, a short side structure and a connection structure, and the first J-shaped gate structure is an integrally formed structure.