Semiconductor device

A semiconductor device, comprising:

• a semiconductor stack body including an upper stack body having an intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers stacked alternately on an upper surface of the intermediate semiconductor layer, a lower stack body having first lower semiconductor layers and second lower semiconductor layers stacked alternately on a lower surface of the intermediate semiconductor layer, and a first conductivity-type impurity region and a second conductivity-type impurity region disposed horizontally;
• a plurality of inactive gate structures arranged at a pitch on a lower surface of the semiconductor stack body;
• at least one recess disposed between at least one pair of adjacent inactive gate structures among the plurality of inactive gate structures and penetrating through the lower stack body from a lower surface of the semiconductor stack body;
• at least one through-hole disposed between at least one pair of adjacent inactive gate structures among the plurality of inactive gate structures and penetrating through the semiconductor stack body;
• at least one first conductivity-type epitaxial pattern disposed in the at least one through-hole and connected to the upper stack body of the semiconductor stack body;
• and
• at least one second conductivity-type epitaxial pattern disposed in the at least one recess and connected to the lower stack body of the semiconductor stack body.

A semiconductor device, comprising:

• a first device region and a second device region disposed horizontally,
• wherein the first device region includes:
• a channel structure including an insulating isolation pattern, first semiconductor patterns vertically stacked and spaced apart from each other on an upper surface of the insulating isolation pattern, and second semiconductor patterns vertically stacked and spaced apart from each other on a lower surface of the insulating isolation pattern;
• a pair of first source/drain patterns disposed on both sides of the channel structure in a first direction and connected to both sides of the first semiconductor patterns, respectively;
• a pair of second source/drain patterns disposed on both sides of the channel structure and connected to both sides of the second semiconductor patterns, respectively;
• a first gate structure extending in a second direction intersecting the first direction and surrounding the first semiconductor patterns;
• and
• a second gate structure intersecting a lower surface of the channel structure, extending in the second direction and surrounding the second semiconductor patterns, and
• wherein the second device region includes:
• a semiconductor stack body disposed on a level corresponding to a level of the channel structure, and including an upper stack body having first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of an intermediate semiconductor layer, and a lower stack body having first lower semiconductor layers and second lower semiconductor layers stacked alternately on a lower surface of the intermediate semiconductor layer, wherein the semiconductor stack body includes a first conductivity-type impurity region and a second conductivity-type impurity region disposed in a horizontal direction;
• a plurality of inactive gate structures arranged on a lower surface of the semiconductor stack body;
• a first conductivity-type epitaxial pattern disposed in a through-hole penetrating through the semiconductor stack body between adjacent inactive gate structures among the plurality of inactive gate structures, and connected to the upper stack body;
• and
• a second conductivity-type epitaxial pattern disposed in a recess formed on a lower surface of the semiconductor stack body between other adjacent inactive gate structures among the plurality of inactive gate structures, and connected to the lower stack body.