Multi-stage amplifier circuits

A multi-stage amplifier circuit, comprising:

• a first multi-stage amplifier circuit and a second multi-stage amplifier circuit,
• the first multi-stage amplifier circuit including
• a second stage N-type transistor connected to a first stage through a 1-1-th capacitor connected to a gate of the second stage N-type transistor,
• a bias N-type transistor connected to a drain of the second stage N-type transistor and having a gate connected to a 1-2-th capacitor,
• a third stage N-type transistor having a gate connected to the drain of the second stage N-type transistor,
• a first current circuit configured to supply a first bias current and a second bias current, and
• a first dynamic switching circuit connected to the second stage N-type transistor, the bias N-type transistor, the third stage N-type transistor, and the first current circuit and configured to sample a voltage corresponding to the first bias current across the 1-1-th capacitor in a first phase and sample a voltage corresponding to the second bias current across the 1-2-th capacitor based on forming a feedback loop comprising the bias N-type and the third stage N-type transistor, and
• the second multi-stage amplifier circuit including
• a second stage P-type transistor connected to the first stage through a 2-1-th capacitor connected to a gate of the second stage P-type transistor,
• a bias P-type transistor connected to a drain of the second stage P-type transistor and having a gate connected to a 2-2-th capacitor,
• a third stage P-type transistor having a gate connected to the drain of the second stage P-type transistor,
• a second current circuit configured to supply the first bias current and the second bias current, and
• a second dynamic switching circuit connected to the second stage P-type transistor, the bias P-type transistor, the third stage P-type transistor, and the second current circuit and configured to sample a voltage corresponding to the first bias current across the 2-1-th capacitor in the first phase and sample a voltage corresponding to the second bias current across the 2-2-th capacitor based on forming a feedback loop comprising the second stage P-type transistor, the bias P-type transistor, and the third stage P-type transistor.