Address fault detection
AssigneeMicron Technology, Inc.
InventorsSteffen Buch, Melissa I. Uribe
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for address fault detection are described. In some examples, a memory device may receive a command (e.g., a write command) and data, and may generate a set of parity bits based on an address of the command and the data. The data and the set of parity bits may be stored to respective portions of a memory array. In some examples, the memory device may receive a command (e.g., a read command) for the data. The memory device may read the data and may generate a set of parity bits (e.g., a second set of parity bits) based on an address of the command and the read data. The sets of parity bits may be compared to determine whether an error associated with the data exists, an error associated with an address path of the memory exists, or both.
Claims20
A memory system, comprising:
- one or more memory devices;
- and
- processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
- write data to a first address of the memory system and a first set of parity bits to a second address of the memory system, wherein the first set of parity bits is based at least in part on the data and the first address;
- read the data from the first address and the first set of parity bits from the second address based at least in part on receiving a read command that indicates the first address;
- generate a second set of parity bits using the data read from the first address and the first address indicated by the read command;
- and
- perform one or more error detection or error correction operations on the data, the first address the data is read from, or any combination thereof, to determine a source of an error based at least in part on determining that the data, the first address the data is read from, or any combination thereof are associated with an error.
A method by a memory system, comprising:
- writing data to a first address of the memory system and a first set of parity bits to a second address of the memory system, wherein the first set of parity bits is based at least in part on the data and the first address;
- reading the data from the first address and the first set of parity bits from the second address based at least in part on receiving a read command that indicates the first address;
- generating a second set of parity bits using the data read from the first address and the first address indicated by the read command;
- and
- performing one or more error detection or error correction operations on the data, the first address the data is read from, or any combination thereof, to determine a source of an error based at least in part on determining that the data, the first address the data is read from, or any combination thereof are associated with an error.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
- write data to a first address of a memory system and a first set of parity bits to a second address of the memory system, wherein the first set of parity bits is based at least in part on the data and the first address;
- read the data from the first address and the first set of parity bits from the second address based at least in part on receiving a read command that indicates the first address;
- generate a second set of parity bits using the data read from the first address and the first address indicated by the read command;
- and
- perform one or more error detection or error correction operations on the data, the first address the data is read from, or any combination thereof, to determine a source of an error based at least in part on determining that the data, the first address the data is read from, or any combination thereof are associated with an error.
Dependencies are inferred from the claim text.