Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
Claims20
A semiconductor memory cell comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said semiconductor memory cell and first and second regions located such that at least a portion of said floating body is located between said first and second regions;
- a nonvolatile memory comprising a resistance change element configured to store said data stored in said capacitorless transistor upon transfer thereto;
- a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
- wherein said buried layer region is commonly connected to at least two of said memory cells;
- wherein said data in said nonvolatile memory is loaded into said capacitorless transistor under at least one of a plurality of predetermined conditions;
- wherein one of said at least one of a plurality of predetermined conditions under which said data in said nonvolatile memory is loaded into said capacitorless transistor comprises restoration of power to said semiconductor memory array.
An integrated circuit comprising:
- a semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell comprises:
- a capacitorless transistor having a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said semiconductor memory cell and first and second regions located such that at least a portion of the floating body is located between said first and second regions;
- a nonvolatile memory comprising a resistance change element configured to store said data stored in said capacitorless transistor upon transfer thereto;
- a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type;
- a buried layer terminal electrically connected to said buried layer region;
- wherein said data in said nonvolatile memory is loaded into said capacitorless transistor under at least one of a plurality of predetermined conditions;
- wherein one of said at least one predetermined conditions under which said data in said nonvolatile memory is loaded into said capacitorless transistor comprises restoration of power to said memory array;
- and
- a control circuit configured to perform said transfer operation.
Dependencies are inferred from the claim text.