Method of making cell regions of integrated circuits

An integrated circuit (IC), comprising:

• a first cell comprising a first active region;
• a second cell comprising a plurality of second active regions, wherein the second cell abuts the first cell, and a height of the second cell is more than twice a height of the first cell;
• and
• a plurality of gate structures extending across each of the first active region and the plurality of second active regions, wherein of a first gate structure of the plurality of gate structures has a gap at an interface between the first cell and the second cell, and the gap is between the first active region and the plurality of second active regions.

An integrated circuit (IC), comprising:

• a first cell comprising a first active region;
• a second cell comprising a plurality of second active regions, wherein the second cell abuts the first cell, and a height of the second cell is greater than a height of the first cell;
• a gate structure extending across each of the first active region and the plurality of second active regions, wherein the gate structure has a first gap at an interface between the first cell and the second cell;
• and
• a continuous poly on oxide definition edge (CPODE) pattern extending across each of the first active region and the plurality of second active regions, wherein the CPODE has a second gap, and the second gap is aligned with the first gap.