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US 2025/0030577 A1Published application
Receiver device for two-wire bus
AssigneeSTMicroelectronics International N.V.
InventorsNicolas Moeneclaey, Gilles Troussel, Christophe Tourniol
Life of this patent
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Abstract
A device includes first and second terminals configured to be respectively connected to first and second conductors of a differential two-wire bus. First and second identical resistive dividing bridges are connected between a reference node and respectively first and second nodes. Third and fourth identical resistive dividing bridges are connected between a supply node and respectively the first and second nodes. A reading circuit is configured to determine a binary state of the bus from the currents flowing through transistors of the reading circuit.
Claims19
A device comprising:
- first and second terminals configured to be respectively connected to first and second conductors of a differential two-wire bus;
- first and second identical resistive dividing bridges connected between a reference node and respectively first and second nodes, wherein the first and second nodes are respectively coupled with the first and second terminals;
- third and fourth identical resistive dividing bridges connected between a supply node and respectively the first and second nodes;
- and
- a reading circuit comprising:
- first and second NMOS transistors having gates connected to each other and sources connected to an intermediary node of the second bridge;
- third and fourth NMOS transistors having gates connected to each other and sources connected to a corresponding intermediary node of the first bridge;
- fifth and sixth PMOS transistors having gates connected to each other and sources connected to an intermediary node of the fourth bridge;
- seventh and eighth transistors having gates connected to each other and sources connected to a corresponding intermediary node of the third bridge;
- wherein the second and third transistors have drains connected to a first current source;
- wherein the sixth and seventh transistors have drains connected to a second current source;
- and
- wherein the reading circuit is configured to determine a binary state of the bus from the currents flowing through the first, fourth, fifth, and eighth transistors.
10 more elements
A reading circuit for a differential two-wire bus device, the reading circuit comprising:
- a first differential pair of NMOS transistors having sources connected to a first intermediate node of a first resistive dividing bridge;
- a second differential pair of NMOS transistors having sources connected to a second intermediate node of a second resistive dividing bridge;
- a third differential pair of PMOS transistors having sources connected to a third intermediate node of a third resistive dividing bridge;
- a fourth differential pair of PMOS transistors having sources connected to a fourth intermediate node of a fourth resistive dividing bridge;
- a first current source connected to drains of one transistor from the first differential pair and one transistor from the second differential pair;
- a second current source connected to drains of one transistor from the third differential pair and one transistor from the fourth differential pair;
- a first biasing circuit configured to apply different biasing potentials to gates of the first and second differential pairs;
- a second biasing circuit configured to apply different biasing potentials to gates of the third and fourth differential pairs;
- and
- a current summing node, wherein the reading circuit is configured to determine a binary state of the bus based on currents flowing through one transistor from each of the four differential pairs to the current summing node.
7 more elements
A device for reading from a differential two-wire bus, comprising:
- a first terminal and a second terminal configured to be respectively connected to first and second conductors of the differential two-wire bus;
- a first resistive dividing bridge connected between a reference node and a first node, wherein the first node is coupled to the first terminal;
- a second resistive dividing bridge connected between the reference node and a second node, wherein the second node is coupled to the second terminal;
- a third resistive dividing bridge connected between a supply node and the first node;
- a fourth resistive dividing bridge connected between the supply node and the second node;
- and
- a reading circuit comprising:
- a first differential pair of NMOS transistors having sources connected to an intermediary node of the second resistive dividing bridge;
- a second differential pair of NMOS transistors having sources connected to an intermediary node of the first resistive dividing bridge;
- a third differential pair of PMOS transistors having sources connected to an intermediary node of the fourth resistive dividing bridge;
- a fourth differential pair of PMOS transistors having sources connected to an intermediary node of the third resistive dividing bridge;
- a first biasing circuit configured to apply different biasing potentials to gates of the first and second differential pairs;
- and
- a second biasing circuit configured to apply different biasing potentials to gates of the third and fourth differential pairs;
- wherein the reading circuit is configured to determine a binary state of the bus based on currents flowing through the first, second, third, and fourth differential pairs.
12 more elements
Dependencies are inferred from the claim text.