Adc architecture incorporating continuous-time quantizer

A circuit, comprising:

• a first integrator having first and second inputs and first and second outputs;
• a switching architecture having first and second inputs and first and second outputs, the first input of the switching architecture coupled to the first output of the first integrator, and the second input of the switching architecture coupled to the second output of the first integrator;
• a second integrator having first and second inputs and first and second outputs, the first input of the second integrator coupled to the switching architecture first output and the second input of the second integrator coupled to the switching architecture second output;
• a quantizer having first and second inputs and a digital output, the first input of the quantizer coupled to the first output of the second integrator, and the second input of the quantizer coupled to the second output of the second integrator;
• and
• a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the digital output of the quantizer.

A method, comprising:

• receiving an analog signal;
• filtering the received signal to form a filtered signal;
• quantizing the filtered signal to determine a digital code representative of the filtered signal, the quantizing performed via a resistor-based successive approximation register (SAR);
• and
• processing the digital code to determine a digital value representative of a value of the analog signal.