Analog-to-digital converter and offset correction method thereof

An offset correction method of an analog-to-digital converter, the method comprising:

• setting the analog-to-digital converter to correction mode;
• applying a common mode voltage to a comparison circuit;
• generating a control bit based on a result of the comparison circuit comparing a first comparison voltage with a second comparison voltage;
• based on a value of the control bit, determining reference voltages to be applied to a correction circuit, from among a plurality of candidate reference voltages;
• generating a correction voltage based on the determined reference voltages by the correction circuit;
• and
• correcting a voltage offset of the comparison circuit by adding the correction voltage to the first comparison voltage.

An analog-to-digital converter (ADC) for converting an input signal into an output signal, the ADC comprising:

• a first digital-to-analog converter (DAC) configured to generate a first comparison voltage based on the input signal, a common mode voltage, a plurality of reference voltages, and a control signal;
• a second DAC configured to generate a second comparison voltage based on the common mode voltage, the plurality of reference voltages, and the control signal;
• a third DAC configured to generate a third comparison voltage based on the common mode voltage, the plurality of reference voltages, and the control signal;
• a first comparison circuit configured to output a first comparison result signal based on a result of comparing the first comparison voltage with the second comparison voltage;
• a second comparison circuit configured to output a second comparison result signal based on a result of comparing the first comparison voltage with a fourth comparison voltage;
• and
• a third comparison circuit configured to output a third comparison result signal based on a result of comparing the first comparison voltage with the third comparison voltage,
• wherein the first DAC comprises:
• a first correction circuit configured to correct respective voltage offsets of the first comparison circuit, the second comparison circuit, and the third comparison circuit based on a result of applying the common mode voltage to the first comparison circuit,
• the second DAC comprises:
• a second correction circuit configured to correct the voltage offset of the second comparison circuit based on a result of applying the common mode voltage to the first comparison circuit, and
• the third DAC comprises:
• a third correction circuit configured to correct the voltage offset of the third comparison circuit based on a result of applying the common mode voltage to the third comparison circuit.