US 2025/0030410 A1 · INTEGRATED CIRCUIT WITH SHMOO DELAY CIRCUIT

Abstract

A first circuit path communicates a first, asynchronous, signal, and a second path communicates a second signal. A schmoo delay circuit receives the first and second signals and includes shmoo control circuitry and a delay generator. The delay generator receives a delay selector signal from the shmoo control circuitry indicative of an amount of delay. The shmoo delay circuit provides a delayed version of at least one of the first or second signals. A first logic circuit receives the delayed version of the at least one of the first signal or the second signal, and a second logic circuit receives another one of the first signal or the second signal. The shmoo control circuitry modifies the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.

Claims20

Dependent claims

An integrated circuit, comprising:

a first circuit path configured to communicate a first signal, wherein the first signal is an asynchronous signal;
a second circuit path configured to communicate a second signal;
a shmoo delay circuit configured to receive the first and second signals and having shmoo control circuitry and a delay generator configured to receive a delay selector signal from the shmoo control circuitry indicative of an amount of delay, the shmoo delay circuit configured to provide a delayed version of at least one of the first signal or the second signal;
a first logic circuit configured to receive the delayed version of the at least one of the first signal or the second signal;
and
a second logic circuit configured to receive another one of the first signal or the second signal, wherein the shmoo control circuitry is configured to modify the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal.

3 more elements

An integrated circuit, comprising:

a first circuit path configured to communicate a first asynchronous reset signal;
a second circuit path configured to communicate a second asynchronous signal;
a shmoo delay circuit configured to receive the first and second signals and having shmoo control circuitry and a delay generator configured to receive a delay selector signal from the shmoo control circuitry indicative of an amount of delay, the shmoo delay circuit configured to provide a delayed version of at least one of the first asynchronous reset signal or the second asynchronous reset signal;
a logic circuit configured to receive the delayed version of the at least one of the first signal or the second signal and configured to generate an output based on both the first asynchronous reset signal and the second asynchronous reset signal, wherein the shmoo control circuitry is configured to modify the delay selector signal to sweep through a set of different delay amounts applied by the delay generator to generate delayed versions of the at least one of the first signal or the second signal;
and
testing circuitry configured to store a selected setting for the delay selector signal corresponding to a selected amount of delay selected as a result of the sweep.

3 more elements

Dependencies are inferred from the claim text.

Integrated circuit with shmoo delay circuit

Life of this patent

Integrated circuit with shmoo delay circuit

Life of this patent

Abstract

Claims20