Level shifting device and method
AssigneeSTMicroelectronics (Grenoble 2) SAS
InventorsDenis COTTIN, Fabrice ROMAIN
Life of this patent
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Abstract
An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.
Claims27
A circuit configured to deliver an output potential level among two first levels according to an input level among two second levels, comprising:
- a first transistor of p-channel type and a second transistor of n-channel type connected at a first node configured to deliver the output potential level, wherein the first and second transistors are electrically in series between second nodes of application of the two first levels;
- a first voltage generator powered by one of the second nodes and configured to deliver a first DC voltage;
- a first control circuit including a first control transistor having a gate to which the first DC voltage is applied and a source directly connected a control terminal of the first transistor, wherein a limit of a gate-to-source control voltage for the first transistor is set by the first DC voltage output plus a threshold turn-on voltage of the first control transistor;
- a second voltage generator powered between the second nodes, controlled by a value representative of the first DC voltage, and configured to deliver a second DC voltage;
- and
- a second transistor control circuit including a second control transistor having a gate to which the second DC voltage is applied and a source directly connected a control terminal of the second transistor, wherein a limit of a gate-to-source control voltage for the second transistor is set by the second DC voltage output and minus a threshold turn-on voltage of the second control transistor.
A circuit, comprising:
- a current source configured to generate a bias current;
- a first diode-connected transistor coupled in series with a diode between a high supply potential node and a first intermediate node biased by said bias current to generate a first DC voltage;
- a mirror transistor coupled to the first transistor and configured to generate a mirror bias current;
- a second diode-connected transistor coupled in series with a diode between a low supply potential node and a second intermediate node biased by said mirror bias current to generate a second DC voltage;
- a first output transistor and a second output transistor connected at an output node, wherein the first and second output transistors are electrically in series between the high supply potential node and the low supply potential node;
- a first drive circuit powered between the high supply potential node and a ground node, wherein the first drive circuit generates a first control signal applied to a control terminal of the first output transistor, said first control signal having a voltage level limit controlled by the first DC voltage;
- and
- a second drive circuit powered between the high supply potential node and the low supply potential node, wherein the second drive circuit generates a second control signal applied to a control terminal of the second output transistor, said second control signal having a voltage level limit controlled by the second DC voltage.
A circuit, comprising:
- a first p-type transistor and a second n-type transistor connected at a first node configured to deliver an output potential level, wherein the first p-type transistor and second n-type transistor are electrically in series between a high supply potential node and a low supply potential node;
- a first voltage generator coupled to the high supply potential node and configured to generate a first DC voltage referenced to the high supply potential node in response to a first bias current, wherein said first DC voltage controls a voltage limit referenced to the high supply potential node for a control voltage applied to a control terminal of the first p-type transistor by a first transistor control circuit;
- and
- a second voltage generator coupled to the low supply potential node and configured to generate a second DC voltage referenced to the low supply potential node in response to a second bias current derived from the first bias current, wherein said second DC voltage controls a voltage limit referenced to the low supply potential node for a control voltage applied to a control terminal of the second n-type transistor by a second transistor control circuit.
Dependencies are inferred from the claim text.