Clock gating circuit for dual-edge-triggered flip-flops
AssigneeQUALCOMM Incorporated
InventorsYimai PENG, Robert Joseph VACHON, Daniel YINGLING, Keith Alan BOWMAN
Life of this patent
Estimating the term…
Abstract
An apparatus, including: a clock gating circuit (CGC), including: a clock gating device configured to selectively gate/pass a selected clock signal based on an enable signal to generate an output clock signal; and a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate the selected clock signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal.
Claims28
An apparatus, comprising:
- a clock gating circuit (CGC), comprising:
- a clock gating device configured to selectively gate or pass a selected clock signal based on an enable signal to generate an output clock signal;
- and
- a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate a select signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal, and
- an exclusive-NOR gate including a first input configured to receive the complementary clock signal, a second input configured to receive the select signal from the clock selection circuit, and an output configured to output the selected clock signal based on the select signal.
(canceled)
(canceled)
An apparatus, comprising:
- a clock gating circuit (CGC), comprising:
- a multiplexer including a first input configured to receive a non-complementary clock signal and a second input configured to receive a complementary clock signal;
- a clock gating device including a first input coupled to an output of the multiplexer and a second input configured to receive an enable signal, the clock gating device comprising
- a transmission gate including an input coupled to the output of the multiplexer, a complementary control input configured to receive a complementary enable signal, and a non-complementary control input configured to receive a non-complementary enable signal,
- a latch inverter including an input coupled to an output of the transmission gate, and
- a latch tristate inverter including an input coupled to an output of the latch inverter, an output coupled to the input of the latch inverter, a complementary control signal configured to receive the non-complementary enable signal, and a non-complementary control signal configured to receive the complementary enable signal;
- and
- a clock selection circuit including a first input coupled to an output of the clock gating device, a second input configured to receive the non-complementary or complementary clock signal, a third input configured to receive the enable signal, and an output coupled to a select input of the multiplexer.
(canceled)
(canceled)
(canceled)
28-30. (canceled)
Dependencies are inferred from the claim text.