Semiconductor memory device

A semiconductor memory device comprising:

• a first chip having a first bonding surface;
• and
• a second chip having a second bonding surface and bonded to the first chip, wherein
• the first chip includes
• a stacked body where a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked in a first direction,
• a memory pillar that penetrates the stacked body in the first direction to form memory cell transistors at intersections with the first conductive layers, and
• a plurality of first bonding electrodes provided on the first bonding surface and to which the second chip is bonded,
• the second chip includes a plurality of second bonding electrodes provided on the second bonding surface and to which the first chip is bonded,
• the plurality of first bonding electrodes and the plurality of second bonding electrodes are joined to each other to form a plurality of joining electrodes,
• the stacked body extends in a second direction intersecting with the first direction and includes a second insulating layer that extends in the first direction in the stacked body such that at least a part of the stacked body is separated in a third direction intersecting with both of the first direction and the second direction,
• the plurality of joining electrodes include a plurality of first joining electrodes and a plurality of second joining electrodes, the first joining electrodes being disposed adjacent to a first side of the second insulating layer in the third direction and at a first predetermined interval along the second direction, and the second joining electrodes being disposed adjacent to a second side of the second insulating layer in the third direction and at a second predetermined interval along the second direction, and
• the plurality of first joining electrodes and the plurality of second joining electrodes are disposed in a staggered arrangement in the second direction and the third direction.