Reducing warpage in a package of stacked integrated circuit dies

A method for fabricating an electronic device, the method comprising:

• disposing, on a substrate having a first coefficient of thermal expansion (CTE), an integrated circuit (IC) die formed on the substrate, the IC die comprising one or more first metal layers having a first thickness;
• disposing, on one of the first metal layers, a plurality of second metal layers having a second thickness, greater than the first thickness, wherein at least one of the second metal layers has a second CTE, greater than the first CTE, in response to an increase in a temperature of the electronic device, the first and second metal layers induce a first stress that acts to cause a warpage at least in the substrate;
• and
• disposing, on one of the second metal layers, a dielectric layer having a third CTE less than the first and second CTEs, in response to the increase in the temperature, the dielectric layer induces, at least in the substrate, a second stress that compensates for at least part of the warpage.

A method for semiconductor device fabrication, the method comprising:

• mounting, on a first carrier substrate, a semiconductor device comprising:
• (i) a substrate having a first coefficient of thermal expansion (CTE), and an integrated circuit (IC) die formed on the substrate, the IC die comprising at least a first metal layer having a first thickness, and at least a second metal layer, which is formed over the first metal layer, the second metal layer having (i) a second thickness, larger than the first thickness, and (ii) a second CTE, larger than the first CTE;
• placing a second carrier substrate on the second metal layer;
• mounting the first carrier substrate on an electrostatic chuck, and applying mechanical force to the second carrier substrate for flattening the semiconductor device;
• and
• applying a thermal treatment to at least the semiconductor device for reducing warpage in the semiconductor device.