Efficient redistribution layer topology

A package for an electronic component, comprising:

• a semiconductor die;
• a passivation layer over the semiconductor die;
• a metal layer on the passivation layer, the metal layer coupled to the semiconductor die through a first conductive via formed in the passivation layer;
• an insulation layer over the metal layer, the insulation layer having an opening extending to the metal layer;
• an under bump metallization layer on the insulation layer, the under bump metallization layer connected to the metal layer through the opening;
• and
• a metallic bump on the under bump metallization layer, the metallic bump coupled to the metal layer through the opening;
• wherein a first horizontal area of the under bump metallization layer is approximately 100 times a second horizontal area of the opening.

A package for an electronic component, comprising:

• a semiconductor die;
• a passivation layer over the semiconductor die;
• a metal layer on the passivation layer, the metal layer coupled to the semiconductor die through a first conductive via formed in the passivation layer;
• an insulation layer over the metal layer, the insulation layer having an opening extending to the metal layer;
• an under bump metallization layer on the insulation layer, the under bump metallization layer connected to the metal layer through the opening;
• and
• a metallic bump on the under bump metallization layer, the metallic bump coupled to the metal layer through the opening;
• wherein a first horizontal area of the opening is approximately 80 times a second horizontal area of the first conductive via.

A flip-chip package for an electronic component, comprising:

• a die having a die surface and a conductive layer at the die surface;
• a passivation layer over and abutting the die surface, the passivation layer having a passivation top surface;
• a first conductive via extending through the passivation layer, the first conductive via having a first via top surface substantially flush with the passivation top surface, and a first via bottom surface that contacts the conductive layer at a first point;
• a metal layer that abuts both the passivation top surface and the first via top surface, the metal layer coupled to the conductive layer by the first conductive via;
• an insulation layer over the metal layer, the insulation layer having an opening extending to the metal layer;
• an under bump metallization (UBM) layer on the insulation layer, the UBM layer extending into the opening and contacting the metal layer at a second point;
• a solder bump on the UBM layer, the solder bump coupled to the metal layer by the UBM layer;
• wherein the passivation layer, the first conductive via, the metal layer, and the insulation layer comprise a redistribution layer (RDL) which extends horizontally from the first point to the second point;
• wherein there is no vertical overlap between the first point and the opening, nor between the first point and the UBM layer;
• wherein the passivation top surface is substantially planar from the first point to the second point;
• and
• wherein a horizontal length dimension of the opening is less than approximately 20 times a horizontal length dimension of the first conductive via.

An electronic device, comprising:

• a printed circuit board (PCB) having conductive terminals;
• plural electronic components electrically coupled to the PCB;
• and a packaged semiconductor device electrically coupled to the conductive terminals of the PCB, the packaged semiconductor device further comprising:
• a semiconductor die having a surface and a conductive layer at the surface;
• a passivation layer over and abutting the surface of the semiconductor die, the passivation layer having a passivation top surface;
• a first conductive via extending through the passivation layer, the first conductive via having a first via top surface substantially flush with the passivation top surface, and a first via bottom surface that contacts the conductive layer at a first point;
• a metal layer that abuts both the passivation top surface and the first via top surface, the metal layer coupled to the conductive layer by the first conductive via;
• an insulation layer over the metal layer, the insulation layer having an opening extending to the metal layer;
• an under bump metallization (UBM) layer on the insulation layer, the under bump metallization layer extending into the opening and contacting the metal layer at a second point;
• a solder mass on the UBM layer, the solder mass coupled to the metal layer by the UBM layer;
• wherein the passivation layer, the conductive via, the metal layer, and the insulation layer comprise a redistribution layer (RDL) which extends horizontally from the first point to the second point;
• wherein there is no vertical overlap between the first point and the opening, nor between the first point and the UBM layer;
• wherein the passivation top surface is substantially planar from the first point to the second point;
• wherein a horizontal length dimension of the opening is less than approximately 20 times a horizontal length dimension of the first conductive via, and
• wherein the solder mass contacts at least one of the conductive terminals of the PCB to provide a portion of an electrical connection between the PCB and the packaged semiconductor device.