US 2025/0029942 A1 · SEMICONDUCTOR PACKAGE

Abstract

A semiconductor package includes a lower structure and an upper structure on the lower structure. The lower structure includes a first substrate, a first through-electrode penetrating the first substrate in a first direction, a first pad connected to the first through-electrode, and a first protective layer surrounding the first pad. The upper structure includes a second substrate, a second through-electrode penetrating the second substrate in the first direction, a second pad connected to the second through-electrode, and a second protective layer surrounding the second pad. The second pad is offset from the first pad in a second direction crossing the first direction. The first pad has a first portion not overlapping the second pad. A first barrier pattern is disposed between the first portion and the second protective layer. A portion of the first barrier pattern is disposed between the first pad and the second pad.

Claims20

Dependent claims

A semiconductor package, comprising:

a lower structure;
and
an upper structure disposed on the lower structure,
wherein the lower structure comprises:
a first substrate;
a first through-electrode that penetrates the first substrate in a first direction;
a first pad connected to the first through-electrode;
and
a first protective layer that surrounds the first pad,
wherein the upper structure comprises:
a second substrate;
a second through-electrode that penetrates the second substrate in the first direction;
a second pad connected to the second through-electrode;
and
a second protective layer that surrounds the second pad,
wherein the second pad is offset from the first pad in a second direction that crosses the first direction,
wherein the first pad includes a first portion that does not overlap the second pad, wherein the semiconductor package further comprises:
a first barrier pattern disposed between the first portion and the second protective layer,
wherein a portion of the first barrier pattern is disposed between the first pad and the second pad.

16 more elements

A semiconductor package, comprising:

a lower structure;
and
an upper structure disposed on the lower structure,
wherein the lower structure comprises:
a first substrate that includes a first device region;
a first through-electrode that penetrates the first substrate in a first direction;
a first pad connected to the first through-electrode;
and
a first protective layer that surrounds the first pad,
wherein the upper structure comprises:
a second substrate that includes the first device region;
a second through-electrode that penetrates the second substrate in the first direction;
a second pad connected to the second through-electrode;
and
a second protective layer that surrounds the second pad,
wherein the second pad is offset from the first pad in a second direction that crosses the first direction and is in contact with the first pad,
wherein the semiconductor package further comprises a first barrier pattern disposed between the first pad and the second pad,
wherein the first barrier pattern includes:
a first barrier portion disposed on an edge of a top surface of the first pad;
a second barrier portion disposed on an edge of a bottom surface of the second pad, wherein the first barrier portion and the second barrier portion partially overlap each other,
a first single portion disposed between the first pad and the second protective layer;
and
an overlap portion disposed between the first pad and the second pad and where the first barrier portion overlaps the second barrier portion, and
wherein a thickness of the first single portion is less than a thickness of the overlap portion.

21 more elements

Dependencies are inferred from the claim text.

Semiconductor package

Life of this patent

Semiconductor package

Life of this patent

Abstract

Claims20