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US 2025/0029932 A1Published application
Semiconductor package
AssigneeLG Innotek Co., Ltd.
InventorsYu Lim CHOE, Tae Gyu KANG, Dong Keon LEE
Life of this patent
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Abstract
A semiconductor package according to an embodiment includes a first insulating layer including a cavity; a connection member buried in the cavity of the first insulating layer; and a molding layer buried in the cavity and surrounding the connection member, wherein a width of the molding layer gradually decreases along a direction from a lower surface of the first insulating layer to an upper surface of the first insulating layer.
Claims20
A circuit board comprising:
- a first insulating layer including a cavity;
- a connection member buried in the cavity of the first insulating layer;
- and
- a molding layer buried in the cavity and surrounding the connection member,
- wherein a width of the molding layer gradually decreases along a direction from a lower surface of the first insulating layer to an upper surface of the first insulating layer.
2 more elements
Dependencies are inferred from the claim text.