Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorYOUNGBAE KIM
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a package substrate, a first device on the package substrate and a second device on the package substrate and horizontally spaced apart from the first device, where the package substrate includes a first redistribution layer, a second redistribution layer on the first redistribution layer, a core section between the first redistribution layer and the second redistribution layer, a dummy structure in the first redistribution layer and on a bottom surface of the core section and a bridge chip in the second redistribution layer and on a top surface of the core section, and where a thermal conductance of the dummy structure is greater than a thermal conductance of the first redistribution layer.
Claims20
A semiconductor package comprising:
- a package substrate;
- a first device on the package substrate;
- and
- a second device on the package substrate and horizontally spaced apart from the first device,
- wherein the package substrate comprises:
- a first redistribution layer;
- a second redistribution layer on the first redistribution layer;
- a core section between the first redistribution layer and the second redistribution layer;
- a dummy structure in the first redistribution layer and on a bottom surface of the core section;
- and
- a bridge chip in the second redistribution layer and on a top surface of the core section, and
- wherein a thermal conductance of the dummy structure is greater than a thermal conductance of the first redistribution layer.
A semiconductor package comprising:
- a package substrate;
- a first device on the package substrate;
- and
- a second device on the package substrate,
- wherein the package substrate comprises:
- a first redistribution layer;
- a second redistribution layer on the first redistribution layer;
- a core section between the first redistribution layer and the second redistribution layer, the core section comprising a central region and a peripheral region at least partially surrounding the central region;
- a plurality of central through vias vertically penetrating the core section in the central region;
- a plurality of peripheral through vias vertically penetrating the core section in the peripheral region;
- a dummy structure in the first redistribution layer and on a bottom surface of the core section;
- and
- a bridge chip in the second redistribution layer and on a top surface of the core section,
- wherein a first width of each of the plurality of central through vias is greater than a second width of each of the plurality of peripheral through vias, and
- wherein a thermal conductance of each of the plurality of central through vias is greater than a thermal conductance of each of the plurality of peripheral through vias.
A semiconductor package comprising:
- a package substrate;
- a first semiconductor chip on the package substrate;
- a chip stack on the package substrate and horizontally spaced apart from the first semiconductor chip, the chip stack comprising a plurality of second semiconductor chips that are vertically stacked;
- and
- a molding layer on the package substrate, the molding layer at least partially surrounding the first semiconductor chip and the chip stack,
- wherein the package substrate comprises:
- a core section;
- a plurality of through vias vertically penetrating the core section;
- a first redistribution layer on a bottom surface of the core section;
- a bridge chip on a top surface of the core section;
- and
- a second redistribution layer at least partially covering the bridge chip and the top surface of the core section, and
- wherein a thermal conductance of the bridge chip is greater than a thermal conductance of the second redistribution layer.
Dependencies are inferred from the claim text.