Semiconductor device having backside gate contact

A device, comprising:

• a substrate;
• a first gate all around transistor on the substrate and including a first channel;
• a second gate all around transistor on the substrate and including a second channel;
• a gate metal wrapped around the first channel and the second channel;
• a shallow trench isolation region in the substrate;
• and
• a backside gate plug extending through the substrate and contacting a gate into the integrated circuit from the backside and contacting the gate metal and the shallow trench isolation region.

A device, comprising:

• a substrate;
• a gate all around transistor on the substrate and including a gate metal;
• an interlevel dielectric layer above the transistors;
• a plurality of source/drain contacts extending through the interlevel dielectric layer;
• a shallow trench isolation region in the substrate;
• a backside gate plug extending through the substrate and contacting the gate metal and the shallow trench isolation region.