Laterally unconfined structure
AssigneeAdeia Semiconductor Bonding Technologies Inc.
InventorCyprian Emeka UZOH
Life of this patent
Estimating the term…
Abstract
Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.
Claims21
(canceled)
A microelectronic assembly, comprising:
- a first element having a substrate and a bonding layer formed on the substrate, wherein the bonding layer has a first bonding surface and comprises:
- an insulating layer;
- a cavity formed in the insulating layer;
- a conductive interconnect structure embedded within the cavity, wherein the first bonding surface comprises a surface of the insulating layer and a surface of the conductive interconnect structure;
- and
- a vertical isolation gap disposed in the insulating layer, wherein the vertical isolation gap at least partially surrounds a perimeter of the conductive interconnect structure and is disposed between one or more sidewalls of the cavity and the conductive interconnect structure;
- and
- a second element having a second bonding surface that is directly bonded to the first bonding surface without an adhesive.
A microelectronic assembly, comprising:
- an insulating layer;
- a cavity formed in the insulating layer;
- a conductive interconnect structure embedded within the cavity, wherein a surface of the insulating layer and a surface of the conductive interconnect structure defined a bonding surface;
- and
- a vertical isolation gap disposed in the insulating layer, wherein the vertical isolation gap at least partially surrounds a perimeter of the conductive interconnect structure and is disposed between one or more of sidewalls of the cavity and the conductive interconnect structure.
A microelectronic assembly, comprising:
- a substrate having a bonding surface;
- a conductive interconnect structure embedded within the cavity and exposed at the bonding surface;
- a vertical isolation gap disposed in the bonding surface and least partially surrounding a perimeter of the conductive interconnect structure, wherein the vertical isolation gap is disposed between one or more sidewalls of the cavity and the conductive interconnect structure;
- and
- an organic fill material in the vertical isolation gap between the conductive interconnect structure and the one or more sidewalls of the cavity.
Dependencies are inferred from the claim text.