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US 2025/0029914 A1Published application
Semiconductor package with backside power delivery network layer
AssigneeSamsung Electronics Co., Ltd.
InventorsHyunsoo CHUNG, Kwang-Soo KIM, Jinchan AHN
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Abstract
A semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.
Claims20
A semiconductor package, comprising:
- a logic die that includes a backside power delivery network layer;
- an interposer die disposed on the logic die;
- a plurality of memory dies stacked on the interposer die;
- and
- a mold layer that covers the interposer die and the memory dies,
- wherein each of the logic die and the interposer die has a first width.
3 more elements
A semiconductor package, comprising:
- a logic die;
- an interposer die disposed on the logic die;
- a plurality of memory dies stacked on the interposer die;
- a mold layer that covers the interposer die and the memory dies;
- and
- a supporting substrate disposed on the memory dies and the mold layer,
- wherein the logic die comprises:
- a backside power delivery network layer;
- a first substrate disposed on the backside power delivery network layer;
- a frontside interconnection layer disposed on the first substrate;
- and
- a first penetration via that penetrates the first substrate and is connected to the backside power delivery network layer,
- wherein each of the memory dies comprises second penetration vias,
- the interposer die comprises third penetration vias that connect the logic die to the memory dies,
- the backside power delivery network layer has a first thickness,
- the frontside interconnection layer has a second thickness that is less than the first thickness,
- each of the memory dies has a third thickness,
- a sum of thicknesses of the logic and interposer dies is greater than the third thickness, and
- a diameter of the third penetration via is greater than a diameter of the second penetration via,
- a number of the third penetration vias is equal to or greater than a number of the second penetration vias,
- the mold layer comprises an oxide material,
- the supporting substrate comprises silicon,
- each of the logic and interposer dies has a first width, and
- the interposer die has a higher thermal conductivity than the logic and memory dies.
21 more elements
A semiconductor package, comprising:
- a package substrate;
- an interposer substrate disposed on the package substrate;
- and
- a first semiconductor chip and a second semiconductor chip disposed on the interposer substrate and arranged side by side in a first direction,
- wherein the second semiconductor chip comprises:
- a logic die that includes a backside power delivery network layer;
- an interposer die disposed on the logic die;
- a plurality of memory dies stacked on the interposer die;
- and
- a mold layer that covers the interposer die and the memory dies,
- wherein the mold layer comprises an oxide material, and
- the interposer die has a higher thermal conductivity than the logic memory dies.
9 more elements
Dependencies are inferred from the claim text.