Semiconductor package and method for fabricating the same

A semiconductor package comprising:

• an interposer;
• a logic die provided on the interposer;
• and
• a high bandwidth memory provided on the interposer,
• wherein the high bandwidth memory comprises:
• a buffer die;
• a first semiconductor chip that is provided on the buffer die, the first semiconductor chip comprising:
• a first semiconductor layer;
• a first connection pad provided on a surface of the first semiconductor layer;
• and
• a first insulation layer provided on the surface of the first semiconductor layer, the surface of the first semiconductor layer extending in a first direction;
• and
• a second semiconductor chip comprising:
• a second semiconductor layer;
• a second connection pad provided on a surface of the second semiconductor layer;
• and
• a second insulation layer provided on the surface of the second semiconductor layer,
• wherein the first connection pad directly contacts the second connection pad,
• wherein the first connection pad is provided on the second connection pad in a second direction that is perpendicular to the first direction,
• wherein the first insulation layer directly contacts the second insulation layer,
• wherein the first insulation layer is provided on the second insulation layer in the second direction, and
• wherein the semiconductor package comprises a molding member that is provided on the buffer die and molds the first semiconductor chip and the second semiconductor chip.

A method of manufacturing a semiconductor package, the method comprising:

• forming a first semiconductor chip comprising a first semiconductor layer;
• a first connection pad, provided on a surface of the first semiconductor layer, and a first insulation layer provided on the surface of the first semiconductor layer, the surface of the first semiconductor layer extending in a first direction;
• forming a second semiconductor chip comprising a second semiconductor layer, a second connection pad provided on a surface of the second semiconductor layer, a second insulation layer provided on the surface of the second semiconductor layer;
• and
• bonding the first semiconductor chip and the second semiconductor chip such that the first connection pad and the second connection pad directly contact and the first insulation layer and the second insulation layer directly contact,
• wherein a width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.