US 2025/0029882 A1 · SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Abstract

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a substrate including first and second surfaces opposite to each other and a groove recessed from the first surface, a chip within the groove and including an active surface facing a bottom surface of the groove, an inactive surface opposite to the active surface, and a side surface connecting the active surface with the inactive surface, chip pads on the active surface of the chip, a shielding layer including a first sub-shielding layer between the bottom surface of the groove and the active surface of the chip and including openings corresponding to the chip pads, respectively, a third sub-shielding layer on the inactive surface of the chip, and a second sub-shielding layer between the side surface of the chip and a side surface of the groove and connecting the first and third sub-shielding layers.

Claims18

Dependent claims

A semiconductor package, comprising:

a substrate comprising a first surface and a second surface opposite to the first surface, the substrate having a groove recessed from the first surface;
a chip within the groove, the chip comprising an active surface facing a bottom surface of the groove, an inactive surface opposite to the active surface, and a side surface connecting the active surface with the inactive surface, a plurality of chip pads on the active surface of the chip;
and
a shielding layer comprising a first sub-shielding layer, a second sub-shielding layer, and a third sub-shielding layer, the first sub-shielding layer between the bottom surface of the groove and the active surface of the chip, the third sub-shielding layer on the inactive surface of the chip, and the second sub-shielding layer between the side surface of the chip and a side surface of the groove and connecting the first sub-shielding layer with the third sub-shielding layer,
wherein the first sub-shielding layer has a plurality of openings corresponding to the plurality of chip pads, respectively.

2 more elements

A method of manufacturing a semiconductor package, comprising:

preparing a substrate comprising a first surface and a second surface opposite to the first surface;
forming a groove recessed from the first surface in the substrate;
forming a first preliminary sub-shielding layer and a second sub-shielding layer covering a bottom surface and a side surface of the groove, respectively, the first preliminary sub-shielding layer and the second sub-shielding layer being connected to each other;
forming a plurality of openings for exposing the bottom surface of the groove in the first preliminary sub-shielding layer to form a first sub-shielding layer;
placing a chip comprising an active surface, an inactive surface opposite to the active surface, and a side surface connecting the active surface with the inactive surface, in the groove such that the active surface of the chip faces the bottom surface of the groove, and a plurality of chip pads disposed on the active surface of the chip correspond to the plurality of openings, respectively;
and
forming a third sub-shielding layer connected to the second sub-shielding layer on the inactive surface of the chip.

4 more elements

Dependencies are inferred from the claim text.

Semiconductor package and method of manufacturing the same

Life of this patent

Semiconductor package and method of manufacturing the same

Life of this patent

Abstract

Claims18