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US 2025/0029879 A1Published application
Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsDongkuk Lee, Yeongseon Kim
Life of this patent
Estimating the term…
Abstract
Disclosed is a semiconductor package comprising a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip may include an upper bonding pad, an upper test pad, and an upper dielectric layer that surrounds the upper bonding pad and the upper test pad. The second semiconductor chip includes a lower bonding pad in contact with the upper bonding pad, a lower test pad in contact with the upper test pad, and a lower dielectric layer that surrounds the lower bonding pad and the lower test pad.
Claims20
A semiconductor package, comprising:
- a first semiconductor chip;
- and
- a second semiconductor chip on the first semiconductor chip,
- wherein the first semiconductor chip includes:
- an upper bonding pad;
- an upper test pad;
- and
- an upper dielectric layer that surrounds the upper bonding pad and the upper test pad,
- wherein the second semiconductor chip includes:
- a lower bonding pad in contact with the upper bonding pad;
- a lower test pad in contact with the upper test pad;
- and
- a lower dielectric layer that surrounds the lower bonding pad and the lower test pad,
- wherein the upper test pad includes:
- a first overlapping portion that overlaps the lower test pad;
- and
- a plurality of second overlapping portions that overlap the lower dielectric layer,
- wherein the first overlapping portion is between the plurality of second overlapping portions,
- wherein the lower test pad includes:
- a third overlapping portion that overlaps the first overlapping portion of the upper test pad;
- and
- a plurality of fourth overlapping portions that overlap the upper dielectric layer,
- wherein the third overlapping portion is between the plurality of fourth overlapping portions.
20 more elements
A semiconductor package, comprising:
- a first semiconductor chip;
- and
- a second semiconductor chip on the first semiconductor chip,
- wherein the first semiconductor chip includes an upper bonding pad and an upper test pad,
- wherein the second semiconductor chip includes:
- a lower bonding pad in contact with the upper bonding pad;
- and
- a lower test pad in contact with the upper test pad,
- wherein the upper test pad includes:
- a plurality of first long sidewalls that extend in parallel to each other;
- and
- a plurality of first short sidewalls that extend in parallel to each other,
- wherein the lower test pad includes:
- a plurality of second long sidewalls that extend in parallel to each other;
- and
- a plurality of second short sidewalls that extend in parallel to each other,
- wherein the plurality of first short sidewalls are shorter than the plurality of first long sidewalls, and
- wherein the plurality of second short sidewalls are shorter than the plurality of second long sidewalls.
15 more elements
A semiconductor package, comprising:
- a first semiconductor chip;
- and
- a second semiconductor chip on the first semiconductor chip,
- wherein the first semiconductor chip includes:
- a first lower dielectric layer;
- a first wiring structure on the first lower dielectric layer;
- a first substrate on the first wiring structure;
- a through via that penetrates the first substrate;
- an upper dielectric layer on the first substrate;
- and
- an upper bonding pad and an upper test pad that are surrounded by the upper dielectric layer,
- wherein the second semiconductor chip includes:
- a lower bonding pad in contact with the upper bonding pad;
- a lower test pad in contact with the upper test pad;
- a second lower dielectric layer that surrounds the lower bonding pad and the lower test pad;
- a second wiring structure on the second lower dielectric layer;
- and
- a second substrate on the second wiring structure,
- wherein the upper test pad includes:
- a first overlapping portion in contact with the lower test pad;
- and
- a plurality of second overlapping portions in contact with the second lower dielectric layer, and
- wherein a sidewall of the first overlapping portion is coplanar with sidewalls of the plurality of second overlapping portions.
20 more elements
Dependencies are inferred from the claim text.