Method for fabricating semiconductor device with damascene structure by using etch stop layer

A method for fabricating a semiconductor device, comprising:

• providing a photomask comprising:
• a translucent layer on a mask substrate and comprising a mask opening of via feature which exposes a portion of the mask substrate;
• and
• an opaque layer on the translucent layer and comprising a mask opening of trench feature which exposes a portion of the translucent layer and the portion of the mask substrate;
• providing a device stack comprising a first dielectric layer on a substrate, a second etch stop layer on a substrate, a first dielectric layer on the second etch stop layer, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer, wherein an etch rate to each of the first etch stop layer and the second etch stop layer is different from an etch rate to each of the first dielectric layer and the second dielectric layer;
• forming a pre-process mask layer on the device stack;
• patterning the pre-process mask layer using the photomask to form a patterned mask layer comprising a mask region corresponding to the opaque layer, a trench region corresponding to the portion of the translucent layer, and a via hole corresponding to the mask opening of via feature, wherein a thickness of the trench region is less than a thickness of the mask region;
• performing a damascene etching process to form a via opening along the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench opening in the second dielectric layer, wherein the trench opening has a bottom on the first etch stop layer;
• and
• forming a via member in the via opening and a trench member in the trench opening;
• wherein the damascene etching process is performed in different stages;
• wherein during a first stage of the damascene etching process, the etch rate of the second dielectric layer is higher than an etch rate of the first etch stop layer;
• wherein during a second stage of the damascene etching process, the etch rate of the first etch stop layer is higher than an etch rate of the first dielectric layer.