Integrated random access memory using inverter loops
AssigneeTaalas Inc.
InventorLjubisa Bajic
Life of this patent
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Abstract
Methods and systems which involve computer memories are disclosed herein. The methods and systems involve integrated Random Access Memory (RAM) using loops of inverters. A disclosed RAM comprises a set of loops of inverters. The loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses. The RAM further comprises a write circuit configured to write a value to a first loop of inverters when provided with a corresponding address for the first loop of inverters. The first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses. The RAM further comprises a read circuit configured to read the value from the first loop of inverters when provided with the corresponding address.
Claims20
A random access memory comprising:
- a set of loops of inverters, wherein the loops of inverters in the set of loops of inverters are addressable using a set of corresponding addresses;
- a write circuit configured to write a value to a first loop of inverters when provided with a corresponding address for the first loop of inverters, wherein the first loop of inverters is in the set of loops of inverters and the corresponding address is in the set of corresponding addresses;
- and
- a read circuit configured to read the value from the first loop of inverters when provided with the corresponding address.
A random access memory comprising:
- an array of loops of inverters wherein the loops of inverters in the array of loops of inverters are independently readable and independently writable using a set of corresponding addresses;
- at least one write circuit configured to set an oscillation state of the loops of inverters independently using the set of corresponding addresses;
- and
- at least one read circuit configured to sense the oscillation state of the loops of inverters independently using the set of corresponding addresses.
A random access memory comprising:
- an array of loops of inverters wherein the loops of inverters in the array of loops of inverters are independently readable and independently writable using a set of corresponding addresses;
- a means for writing values to the loops of inverters independently using the set of corresponding addresses;
- and
- a means for reading the values from the loops of inverters independently using the set of corresponding addresses.
Dependencies are inferred from the claim text.