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US 2025/0029664 A1Published application
Circuit and method for on-chip leakage detection and compensation for memories
AssigneeSTMicroelectronics International N.V.
InventorsArpit VIJAYVERGIA, Vikas RANA
Life of this patent
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Abstract
An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
Claims20
A method, comprising:
- precharging a sensing bitline for a read operation of a memory cell coupled to the sensing bitline;
- sensing a first leakage current on the sensing bitline while precharging the sensing bitline;
- evaluating, with a sense amplifier after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline;
- and
- compensating for the first leakage current while evaluating the data value by generating a first leakage compensation current with a leakage current compensation circuit.
2 more elements
An integrated circuit, comprising:
- a memory cell;
- a sensing bitline coupled to the memory cell, wherein the sensing bitline is precharged for a read operation of the memory cell;
- a leakage current compensation circuit coupled to the sensing bitline, wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged;
- and
- a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline, and
- wherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated.
3 more elements
A system, comprising:
- a memory array including a plurality of memory cells;
- a sensing bitline coupled to a memory cell of the plurality of memory cells, wherein the sensing bitline is precharged for a read operation of the memory cell;
- a leakage current compensation circuit coupled to the sensing bitline, wherein the leakage current compensation circuit is configured to sense a first leakage current on the sensing bitline while the sensing bitline is precharged;
- and
- a sense amplifier configured to evaluate, after precharging the sensing bitline, a data value of the memory cell based on a sensing current on the sensing bitline and output the data value, and
- wherein the leakage current compensation circuit configured to generate a first leakage compensation current for compensating the first leakage current while the data value is evaluated.
3 more elements
Dependencies are inferred from the claim text.