Memory and access method therefor, and electronic device
AssigneeBeijing Superstring Academy of Memory Technology
InventorsZhengyong ZHU, Bokmoon KANG, Dan WANG, Chao ZHAO
Life of this patent
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Abstract
Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.
Claims21
A memory, comprising:
- at least one memory array;
- and
- at least one control circuit,
- wherein the at least one memory array comprises a plurality of memory cells arranged in an array as well as a plurality of read wordlines and a plurality of read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor, with a gate of the second transistor connected to a first electrode of the first transistor, a first electrode of the second transistor connected to a read wordline, and a second electrode of the second transistor connected to a read bitline,
- wherein the at least one control circuit is connected to the read wordline and the read bitline, and
- the at least one control circuit is configured to:
- transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline;
- transmit, during a pre-charging stage, a second voltage to the read bitline;
- and
- transmit, during a read-sensing stage, a third voltage to the read wordline.
(canceled)
An electronic device, comprising:
- a memory, wherein the memory comprises:
- at least one memory array;
- and
- at least one control circuit,
- wherein the at least one memory array comprises a plurality of memory cells arranged in an array as well as a plurality of read wordlines and a plurality of read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor, with a gate of the second transistor connected to a first electrode of the first transistor, a first electrode of the second transistor connected to a read wordline, and a second electrode of the second transistor connected to a read bitline,
- wherein the at least one control circuit is connected to the read wordline and the read bitline, and
- the at least one control circuit is configured to:
- transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline;
- transmit, during a pre-charging stage, a second voltage to the read bitline;
- and
- transmit, during a read-sensing stage, a third voltage to the read wordline.
A method for accessing a memory, comprising:
- pre-processing, during a pre-processing stage, a memory array and transmitting a first voltage to a plurality of read wordlines and a plurality of read bitlines, wherein the memory array comprises a plurality of memory cells arranged in an array;
- pre-charging, during a pre-charging stage, the read bitlines connected to memory cells, wherein a pre-charging voltage is a second voltage;
- and
- outputting, during a read-sensing stage, a third voltage to the read wordlines connected to the memory cells, and accessing the memory cells based on changes in electrical signals on the read bitlines.
Dependencies are inferred from the claim text.