Computation in-memory using 6-transistor bit cells

A device, comprising:

• a first bit cell configured to store a first filter weight;
• a second bit cell configured to store a second filter weight;
• and
• a multiply and average (MAV) circuit coupled to the first and second bit cells, the MAV circuit having an input and configured to:
• charge a first capacitor and a second capacitor to a voltage at the input;
• and
• discharge one of the first capacitor or the second capacitor responsive to at least one of the first filter weight or the second filter weight.

A device, comprising:

• a first bit cell configured to store a first filter weight;
• a second bit cell configured to store a second filter weight;
• and
• a multiply and average (MAV) circuit coupled to the first and second bit cells, the MAV circuit coupled to a positive input, a negative input, a positive output, and a negative output, and the MAV configured to:
• charge a first capacitor to a first voltage at the positive input;
• charge a second capacitor to a second voltage at the negative input;
• connect one of the first capacitor or the second capacitor to the positive output responsive to at least one of the first filter weight or the second filter weight;
• and
• connect the other one of the first capacitor or the second capacitor to the negative output responsive to at least one of the first filter weight or the second filter weight.

A method, comprising:

• receiving, by a multiply and average (MAV) circuit, a voltage;
• charging, by the MAV circuit, a first capacitor and a second capacitor to the voltage;
• discharging, by the MAV circuit, one of the first capacitor and the second capacitor responsive to at least one of a first filter weight in a first bit cell or a second filter weight in a second bit cell;
• and
• discharging, by the MAV circuit, one of the first capacitor and the second capacitor responsive to at least one of the first filter weight or the second filter weight.

A method, comprising:

• receiving, by a multiply and average (MAV) circuit, a first voltage at a positive input and a second voltage at a negative input;
• charging, by the MAV circuit, a first capacitor to the first voltage;
• charging, by the MAV circuit, a second capacitor to the second voltage;
• connecting, by the MAV circuit, one of the first capacitor or the second capacitor to a positive output responsive to at least one of a first filter weight in a first bit cell or a second filter weight in a second bit cell;
• and
• connecting, by the MAV circuit, another one of the first capacitor or the second capacitor to a negative output responsive to at least one of the first filter weight or the second filter weight.