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US 2025/0029643 A1Published application
Memory module related to signal integrity of clock
AssigneeSK hynix Inc.
InventorChoung Ki SONG
Life of this patent
Estimating the term…
Abstract
A memory module includes a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval. The clock driver adjusts the clock delay interval by comparing the phase of the division clock and the phase of a feedback division clock that is generated from the internal clock.
Claims20
A memory module comprising:
- a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval,
- wherein the clock driver adjusts the clock delay interval by comparing a phase of the division clock and a phase of a feedback division clock that is generated from the internal clock.
A memory module comprising:
- a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval,
- wherein the clock driver adjusts the clock delay interval by comparing a phase of an external buffer clock that is generated from the external clock and a phase of a feedback buffer clock that is generated from the internal clock.
A memory module comprising:
- a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval,
- wherein the clock driver comprises:
- a first phase detection circuit configured to generate a first delay control signal by comparing phases of the division clock and a feedback division clock;
- a first clock delay circuit configured to generate a first selection delay division clock by delaying the division clock by a first clock delay interval that is set based on the first delay control signal and a driving control signal;
- a second phase detection circuit configured to generate a second delay control signal by comparing the phases of the division clock and the feedback division clock;
- and
- a second clock delay circuit configured to generate a second selection delay division clock by delaying the division clock by a second clock delay interval that is set based on the second delay control signal and the driving control signal.
4 more elements
A memory module comprising:
- a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying a division clock that is generated from the external clock by a clock delay interval,
- wherein the clock driver comprises:
- a phase detection circuit configured to generate a delay control signal by comparing phases of the division clock and a feedback division clock;
- a first clock delay circuit configured to generate a first selection delay division clock by delaying the division clock by a first clock delay interval that is set based on the delay control signal and a driving control signal;
- and
- a second clock delay circuit configured to generate a second selection delay division clock by delaying the division clock by a second clock delay interval that is set based on the delay control signal and the driving control signal.
3 more elements
A memory module comprising:
- a clock driver configured to receive an external clock through a module pin and configured to generate an internal clock that is transmitted to memory chips by delaying an external buffer clock that is generated from the external clock by a clock delay interval,
- wherein the clock driver adjusts the clock delay interval by comparing a phase of the external buffer clock and a phase of a feedback buffer clock that is generated from the internal clock.
Dependencies are inferred from the claim text.