Shift register unit, gate driver circuit, and display device

A shift register unit, comprising:

• a first input transistor, wherein a gate of the first input transistor is coupled to a first clock terminal, a first electrode of the first input transistor is coupled to an input terminal, and a second electrode of the first input transistor is coupled to a first node, and the first input transistor is configured to control connection or disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal;
• a second input transistor, wherein a gate and a first electrode of the second input transistor are coupled to a second node, and a second electrode of the second input transistor is coupled to the first node, and the second input transistor is configured to control connection or disconnection between the second node and the first node in response to a potential at the second node;
• a second input circuit, coupled to the first node, the first clock terminal and a third node, and configured to control connection or disconnection between the first clock terminal and the third node in response to a potential at the first node;
• a first control circuit, coupled to the input terminal, the first clock terminal and the second node, and configured to control connection or disconnection between the input terminal and the second node in response to the first clock signal;
• a second control circuit, coupled to the third node, a second clock terminal, the first node, a first power terminal, a fourth node and a fifth node, and configured to control connection or disconnection between the second clock terminal and the fourth node in response to a potential at the third node and a second clock signal provided by the second clock terminal, and control the first node to be connected to the fifth node in response to a first power signal provided by the first power terminal;
• and
• an output circuit, coupled to the fourth node, the fifth node, the first power terminal, a second power terminal and an output terminal, and configured to control connection or disconnection between the second power terminal and the output terminal in response to a potential at the fourth node, and control connection or disconnection between the first power terminal and the output terminal in response to a potential at the fifth node.

A gate driver circuit, comprising:

• at least two cascaded shift register units;
• wherein
• each of the at least two cascaded shift register units comprises:
• a first input circuit, coupled to a first clock terminal, an input terminal, a first node and a second node, and configured to control connection or disconnection between the input terminal and the first node in response to a first clock signal provided by the first clock terminal, and control connection or disconnection between the second node and the first node in response to a potential at the second node;
• a second input circuit, coupled to the first node, the first clock terminal, a first power terminal and a third node, and configured to control connection or disconnection between the first clock terminal and the third node in response to a potential at the first node, and control connection or disconnection between the first power terminal and the third node in response to the first clock signal;
• a first control circuit, coupled to the input terminal, the first clock terminal, the second node, a second power terminal, a second clock terminal and the third node, and configured to control connection or disconnection between the input terminal and the second node in response to the first clock signal, control connection or disconnection between the second power terminal and the second node in response to a potential at the third node, and control connection or disconnection between the second clock terminal and the second node in response to the potential at the second node;
• a second control circuit, coupled to the third node, the second clock terminal, the first node, the first power terminal, the second power terminal, a fourth node and a fifth node, and configured to control connection or disconnection between the second clock terminal and the fourth node in response to the potential at the third node and a second clock signal provided by the second clock terminal, control connection or disconnection between the second power terminal and the fourth node in response to the potential at the first node, and control the first node to be connected to the fifth node in response to a first power signal provided by the first power terminal;
• and
• an output circuit, coupled to the fourth node, the fifth node, the first power terminal, the second power terminal and an output terminal, and configured to control connection or disconnection between the second power terminal and the output terminal in response to a potential at the fourth node, and control connection or disconnection between the first power terminal and the output terminal in response to a potential at the fifth node;
• and an input terminal of a first stage of shift register unit is coupled to an input enable terminal, and in other stages of shift register units other than the first stage of shift register unit, an input terminal of each stage of shift register unit is coupled to an output terminal of a cascaded previous stage of shift register unit.