Shift register unit, gate driving circuit and display substrate

A shift register unit, comprising:

• a first sensing control input circuit connected to a sensing control node, a sensing signal input terminal, a random signal input terminal, a clock control signal input terminal, and a first pull-up node;
• and configured to write a signal from the sensing signal input terminal to the sensing control node in response to control of a valid level signal from the random signal input terminal, and write a valid level signal to the first pull-up node in response to control of a valid level signal at the sensing control node and a valid level signal from the clock control signal input terminal;
• and
• at least one first output circuit, each of which is connected to the first pull-up node, a first clock signal input terminal, and a first signal output terminal;
• and configured to write a signal from the first clock signal input terminal to the first signal output terminal in response to control of a valid level signal at the first pull-up node;
• wherein the shift register unit further comprises:
• a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit;
• the first voltage control circuit is connected to a first power supply terminal, the first pull-up node and a first voltage control node, and is configured to write a valid level signal from the first power supply terminal to the first voltage control node in response to control of a valid level signal at the first pull-up node;
• the first sensing control input circuit is connected to the first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to the first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to form a path between the first sensing input leakage prevention node and the first pull-up node in response to control of a valid level signal at the clock control signal input terminal, and to disconnect the first sensing input leakage prevention node from the first pull-up node in response to control of an invalid level signal at the clock control signal input terminal;
• and
• the first current limiting circuit is connected to the first voltage control node.