Parallelizing techniques for in-memory compute architecture
OwnerAndrew John Gillinventor
Life of this patent
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OwnerAndrew John Gillinventor
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A method is described. The method includes profiling a learning network. The learning network includes compute tile(s) and a model. A compute tile includes compute engines and a general-purpose (GP) processor. Each compute engine includes a compute-in-memory (CIM) hardware module. The model includes convolutions and activation functions. The convolutions correspond to the compute engines. The method also includes determining, based on the profiling, a reschedule operation for a convolution of the convolutions. The reschedule operation provides multiple tensors based on an input tensor for the convolution. The tensors are configured to undergo at least a portion of the convolution in accordance with a temporal distribution. The method also includes performing, on the learning network and using the reschedule operation, a forward pass for input data
A method, comprising:
A compute tile, comprising:
A compute program product, embodied in a non-transitory computer readable medium and comprising computer instructions for:
Dependencies are inferred from the claim text.